Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller

Authors:
F. Lima;L. Carro;R. Velazco;R. Reis
Affiliations:
-;-;-;-
Venue:
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Year:
2002

Citing 0
Cited 2

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A multiple bit upset tolerant SRAM memory

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming Code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was emulated in a Virtex FPGA platform. Results evaluate the robustness of the tolerant 8051 in a multiple upsets environment.