Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
What von Neumann did not say about multiplexing beyond gate failures: the gory details
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
Analysis of defect tolerance in molecular crossbar electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic error modeling for nano-domain logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In the emerging nanotechnologies, faulty components may be an integral part of a system. For the system to be reliable, the error of the building blocks has to be smaller than a threshold. Therefore, finding exact error thresholds for noisy gates is one of the most challenging problems in fault-tolerant computations. Under the von Neumann's probabilistic computing framework, we show that computation by circuits built out of noisy NAND gates with an arbitrary number of K inputs under worst case operation can be readily described by nonlinear discrete maps. Bifurcation analysis of such maps naturally gives the exact error thresholds above which no reliable computation is possible. It is further shown that the maximum threshold value for a K-input NAND gate is obtained when K=5. This implies that if one chooses NAND gate as basic building blocks, then the optimal number of inputs for the NAND gate may be very different from the conventional value of 2. The analysis technique generalizes to other types of gates and circuits that use voting to improve reliability, as well as a network built out of the so-called para-restituted NAND gates recently proposed by Sadek et al. Nonlinear dynamics theory offers an interesting perspective to study rich nonlinear interactions among faulty components and design nanoscale fault-tolerant architectures.