The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Towards an active network architecture
ACM SIGCOMM Computer Communication Review
Practical Byzantine fault tolerance
OSDI '99 Proceedings of the third symposium on Operating systems design and implementation
Directed diffusion: a scalable and robust communication paradigm for sensor networks
MobiCom '00 Proceedings of the 6th annual international conference on Mobile computing and networking
The Manchester Mark I and atlas: a historical perspective
Communications of the ACM - Special issue on computer architecture
Reverse path forwarding of broadcast packets
Communications of the ACM
Exploring and exploiting wire-level pipelining in emerging technologies
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
An instruction set and microarchitecture for instruction level distributed processing
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Programming the EDSAC: Early Programming Activity at the University of Cambridge
IEEE Annals of the History of Computing
IEEE Transactions on Parallel and Distributed Systems
Dynamic binary translation for accumulator-oriented architectures
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Teramac Custom Computer: Extending the Limits with Defect Tolerance
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Future Challenges in VLSI Design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Self-assembled computer architecture: design and fabrication theory
Self-assembled computer architecture: design and fabrication theory
Using Circuits and Systems-Level Research to Drive Nanotechnology
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
The design of DNA self-assembled computing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Exploring technology alternatives for nano-scale FPGA interconnects
Proceedings of the 42nd annual Design Automation Conference
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
IEEE Design & Test
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
The use of nanoelectronic devices in highly parallel computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
A defect tolerant self-organizing nanoscale SIMD architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A self-organizing defect tolerant SIMD architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Architectural implications of nanoscale integrated sensing and computing
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Industry perspectives: wireless ad hoc nanoscale networking
IEEE Wireless Communications - Special issue on seamless content delivery in the future mobile internet
Routing in self-organizing nano-scale irregular networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Toward in vivo nanoscale communication networks: utilizing an active network architecture
Frontiers of Computer Science in China
A first effort for a distributed segment-based approach on self-assembled nano networks
Proceedings of the Sixth International Workshop on Network on Chip Architectures
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This article explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are (1) limited node size, (2) random node interconnection, and (3) high defect rates. We present and evaluate an accumulator-based active network architecture that is compatible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly.