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In the current and coming decades VLSI design - whichcurrently enables us to build million-transistor chips - willbecome Gigascale (GSI) design and Terascale ScaleIntegration (TSI) design, respectively. In this context,''gigascale'' and ''terascale'' signifies more than onebillion and one trillion devices per chip, respectively.From a system design perspective, this increase inintegration levels is qualitatively different from pastintegration improvements of similar magnitudes. Inparticular, manufacturing defects will increase, deviceswill get less reliable, interconnect will be orders ofmagnitude slower than transistors, new nanotechnologieswill emerge, and signal and power management issueswill be aggravated. It is plausible that newnanotechnologies will be used to complement or replaceCMOS. This paper (and its presentation) discusses someof the unique system design challenges posed byanticipated nanoscale CMOS and molecular electronicstechnologies, and presents some ground-breakingsuggestions of novel system-level approaches to deal withthese challenges.