Application-independent defect tolerance of reconfigurable nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-independent defect-tolerant crossbar nano-architectures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
Journal of Electronic Testing: Theory and Applications
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects
Journal of Systems Architecture: the EUROMICRO Journal
BISM: built-in self map for hybrid crossbar nano-architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-overhead defect tolerance in crossbar nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reliability aware yield improvement technique for nanotechnology based circuits
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Nanoscale digital computation through percolation
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
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Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up self-assembly fabrication process results in a significantly higher defect density compared to conventional lithography-based process. Defect tolerance techniques are therefore essential to obtain an acceptable manufacturing yield. In this paper we investigate defect tolerance properties of a two-dimensional (2D) nano-scale crossbar, which is the basic block of various nano architectures which have been recently proposed. Various nano-wire and switch faults are studied and their impact on the routability of a crossbar are investigated. In the presenceof defects, it is still possible to utilize a defective crossbar at reduced functionality, i.e. as a smaller defect-free crossbar. Simulation results for different sizes and defect densities are presented. This proposed approach can be utilized by architecture designers to determine the expected size of functional (defect-free) crossbar based on defect density information obtained from the fabrication process.