NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A Case for CMOS/nano co-design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Computer
Defect tolerant probabilistic design paradigm for nanotechnologies
Proceedings of the 41st annual Design Automation Conference
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Simulation of spatial fault distributions for integrated circuit yield estimations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Augmentation of SPICE for simulation of circuits containing resonant tunneling diodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely to have many imperfections and variations; thus, defect tolerance is considered as one of the most exigent challenges. In this paper, we evaluate three different logic mapping algorithms with defect tolerance to circumvent clustered defective crosspoints in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations. Then, costs associated with the repair process are analyzed and a method to find the most cost-effective repair solution is presented.