Simulation of spatial fault distributions for integrated circuit yield estimations

• Authors: C. H. Stapper
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

Two methods used in fault simulation for integrated circuit modeling are described. Both methods simulate clustered fault locations on a map. In the first approach, the clusters are initially generated using a radial Gaussian probability distribution. The results are consequently passed through cluster shaping programs, which produce clusters that resemble those observed on actual integrated circuit wafers. In the second approach, faults are added to the chips as a function of time. The probability that additional faults are created during any interval of time is assumed to be related to the number of faults already on the chip, as well as the number of faults on adjacent chips. This technique generates frequency distributions of the number of faults per chip that closely resemble those observed in actual integrated circuits