On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Pattern Recognition Letters - Special issue: Artificial neural networks in pattern recognition
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Journal of Electronic Testing: Theory and Applications
Simulation of spatial fault distributions for integrated circuit yield estimations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Journal of Electronic Testing: Theory and Applications
Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking
ITC '12 Proceedings of the 2012 IEEE International Test Conference (ITC)
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
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Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, compact device dimension, etc. Wafer-on-wafer stacking offers practical advantages in 3D IC fabrication, but it suffers from low compound yield. To improve the yield, a novel manipulation scheme of wafer named n-sector symmetry and cut (SSCn) is proposed. In this method, wafers with rotational symmetry are cut into n identical sectors, where n is a suitably chosen integer. The sectors are then used to replenish repositories. The SSCn method is combined with best-pair matching algorithm for compound yield evaluation. Simulation of wafers with nine different defect distributions shows that previously known plain rotation of wafers offers only a trivial benefits in yield. A cut number four is optimal for most of the defect models. The SSC4 provides significantly higher yield and the advantage becomes more obvious with increase of the repository size and the number of stacked layers. Cost model of SSCn is analyzed and the cost-effectiveness of SSC4 is established. Observations made are: 1) Cost benefits of SSC4 become larger as the manufacturing overhead of SSC4 become smaller, 2) cost improvement of SSC4 over conventional basic method increases as the number of stacked layers increases and 3) for most defect models, SSC4 largely reduces the cost even when manufacturing overhead of SSC4 is considered to be very large.