Journal of Electronic Testing: Theory and Applications
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We present and evaluate a simulation methodology to model the impact of the radial clustering of defects on wafers on the yield of 3D ICs manufactured using wafer to wafer stacking. Our simulations draw on an extensively validated model for radial yield degradation on wafers from the literature to incorporate the effect of this key contributor to the widely observed clustering of defects on semiconductor wafers. Current 3D-SIC yield estimation methods ignore defect clustering and assume a uniform distribution of defective dies on each wafer. Our results show that the radial clustering of defective dies causes stacked die yields to be significantly higher than that projected by current models. For 4–5 layer stacks the difference can be 50% or more. Our simulation studies are further validated by comparison with actual silicon data, which suggests that even the more accurate yield estimates from our improved methodology may be somewhat pessimistic. Thus the results presented here show that in practice degradation in stacked die yield from compounding may not be as severe as commonly estimated. This has significant implications in evaluating cost trade-offs associated with 3D-SIC manufacturing.