Unsupervised spatial pattern classification of electrical-wafer-sorting maps in semiconductor manufacturing

Authors:
F. Di Palma;G. De Nicolao;G. Miraglia;E. Pasquinetti;F. Piccinini
Affiliations:
Dipartimento di Informatica e Sistemistica, Universití di Pavia, Via Ferrata 1, 27100 Pavia, Italy;Dipartimento di Informatica e Sistemistica, Universití di Pavia, Via Ferrata 1, 27100 Pavia, Italy;STMicroelectronics Via C. Olivetti 2, 20041 Agrate Brianza, Italy;STMicroelectronics Via C. Olivetti 2, 20041 Agrate Brianza, Italy;STMicroelectronics Via C. Olivetti 2, 20041 Agrate Brianza, Italy
Venue:
Pattern Recognition Letters - Special issue: Artificial neural networks in pattern recognition
Year:
2005

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Abstract

In semiconductor manufacturing, the spatial pattern of failed devices in a wafer can give precious hints on which step of the process is responsible for the failures. In the literature, Kohonen's Self Organizing Feature Maps (SOM) and Adaptive Resonance Theory 1 (ART1) architectures have been compared, concluding that the latter are to be preferred. However, both the simulated and the real data sets used for validation and comparison were very limited. In this paper, the use of ART1 and SOM as wafer classifiers is re-assessed on much more extensive simulated and real data sets. We conclude that ART1 is not adequate, whereas SOM provide completely satisfactory results including visually effective representation of spatial failure probability of the pattern classes.