Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure

Authors:
Mohammad Tehranipoor
Affiliations:
University of Maryland, Baltimore
Venue:
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Year:
2005

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Abstract

A BIST procedure is proposed for testing and fault tolerance of molecular electronics-based nanoFabrics. The nanoFabrics are assumed to include up to 1010 gates; this requires new test strategies that can efficiently test and diagnose the nanoFabric in a reasonable time. Our BIST procedure utilizes nanoFabric驴s components as test pattern generator and response analyzer. The proposed technique tests the components in parallel with a low number of test configurations reducing the test time significantly. Due to high defect density of nanoFabrics, a diagnostic procedure needs to be done to achieve a high recovery. A defect database is created to be used by compilers during configuring the nanoFabric to avoid defective components. This results in a reliable system constructed using unreliable components.