Introduction to algorithms
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
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Lithography based IC manufacturing is approaching its physical limits in terms of feature size. In this scenario, nanotechnology based manufacturing, relying on self-assembly of nanotubes or nanowires, has been predicted as an alternative to CMOS technology. However, such processes are expected to have high defect density and therefore must be handled through effective defect tolerant techniques. In this paper, an innovative technique is proposed, which for a given circuit size utilizes different combinations of defect-free crossbars to build the desired circuit with improved yield. The goal of the proposed approach is to increase the number of defect free crossbars and the total yield, by connecting defect free subsets together. The reliability of the resulting circuits has been estimated, and the results have shown that the application of the proposed approach provides significant yield improvement, but also may decrease the reliability due to the growing number of interconnections. To overcome this drawback, a guideline to optimize the architecture by exploring an optimal trade-off between yield and reliability is proposed.