DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Hybrid CMOS Single-Electron-Transistor Device And Circuit Design
Hybrid CMOS Single-Electron-Transistor Device And Circuit Design
Towards an ultra-low-power architecture using single-electron tunneling transistors
Proceedings of the 44th annual Design Automation Conference
Emerging non-CMOS nanoelectronic devices - What are they?
NEMS '09 Proceedings of the 2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems
Low Power Single Electron Or/Nor Gate Operating at 10GHz
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
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IEEE Transactions on Nanotechnology
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This work describes the design of a reconfigurable logic gate array composed of single-electron tunneling (SET) transistors currently under investigation as potential post-CMOS candidates for future nano-scale integrated circuits for use in low-power embedded systems. A layer in the proposed array consists of a SET summing-inverter block replicated in subsequent blocks and extended to implement flexible logic functions in terms of the sum-of-products (SoP) and products-of-sum (PoS) forms. The reconfiguring of the array can be accomplished through the alteration of a block's logic function by way of a control voltage. The reconfigurable array can work normally at room temperature and can flexibly realize functions with better performance at lower power compared with pure MOSFET circuits.