A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the de- sign hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently re- cover from delay errors, which would be inevitably in- troduced due to the use of common-case delay values. Variability-agnostic designs are automatically trans- formed into variability-tolerant circuits by the introduc- tion of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive per- formance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.