Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention flip-flop. Conventional zero standby leakage retention flip-flops have several problems, including difficulty in design optimization among the C - Q delay, sensing current, and process variation tolerance, and the insufficient write current. In this paper, a new MTJ based retention flip-flop is presented to solve these problems. The proposed retention flip-flop is designed using industry-compatible 45-nm process technology model. The proposed retention flip-flop achieves a 41.58% reduced C - Q delay and a 67.53% lowered sensing current with a 1.06% increased area compared to the previous retention flip-flop.