Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Proceedings of the 37th annual international symposium on Computer architecture
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Proceedings of the 38th annual international symposium on Computer architecture
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A non-volatile microcontroller with integrated floating-gate transistors
DSNW '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
RTSS '11 Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium
A compression-based area-efficient recovery architecture for nonvolatile processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Nonvolatile processor (NVP) has become an emerging topic in recent years. The conventional NV processor equips each flip-flop with a nonvolatile storage for data backup, which results in much faster backup speed with significant area overheads. A compression based architecture (PRLC) solved the area problem but with a nontrivial increasing on backup time. This paper provides a segment-based parallel compression (SPaC) architecture to achieve tradeoffs between area and backup speed. Furthermore, we use an off-line and online hybrid method to balance the workloads of different compression modules in SPaC. Experimental results show that SPaC can achieve 76% speed up against PRLC and meanwhile reduces the area by 16% against conventional NV processors.