SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors
Proceedings of the Conference on Design, Automation and Test in Europe
A compression-based area-efficient recovery architecture for nonvolatile processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a non-volatile processor architecture where its entire state can be almost instantly stored and restored in a non-volatile fashion. This capability is attractive for embedded or mobile devices in highly energy constrained environments. The non-volatile microprocessor can enable long computations to continue across power interruptions on self-powered devices or save idle power consumption without sacrificing responsiveness. To realize this vision, a microprocessor must be able to copy state between volatile and non-volatile storage with minimal latency and energy consumption. Our non-volatile architecture addresses this challenge through a per-cell integration of floating-gate non-volatile transistors into volatile state elements and careful system-level optimizations to hide expensive non-volatile operations. We evaluate this approach with a transistor-level prototype of an 8-bit nonvolatile microcontroller. Experiments indicate that the proposed architecture has minimal impact on normal operation while enabling all processor state to be preserved across an unexpected power interruption.