A scalable design methodology for energy minimization of STTRAM: a circuit and architecture perspective

Authors:
Subho Chatterjee;Mitchelle Rasquinha;Sudhakar Yalamanchili;Saibal Mukhopadhyay
Affiliations:
Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

Citing 4
Cited 3

MiBench: A free, commercially representative embedded benchmark suite

WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

Proceedings of the 45th annual Design Automation Conference
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Proceedings of the 45th annual Design Automation Conference
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)

ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

Proceedings of the International Conference on Computer-Aided Design
Write-optimized reliable design of STT MRAM

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
High-performance low-energy STT MRAM based on balanced write scheme

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we analyze the energy dissipation in spin-torque-transfer random access memory array (STTRAM). We present a methodology for exploring the design space to minimize the energy dissipation of the array while maintaining required read and write quality for a given magnetic tunnel junction technology. The proposed method shows the need for proper choice of the silicon transistor width and array operating voltage to minimize the energy dissipation of the STTRAM array. The write energy is found to be 10× greater than read energy. Hence, read-write ratio becomes a crucial factor that determines energy for STTRAM last level caches (L2). An exploration is performed across several architectural benchmarks including shared and non-shared caches for detailed energy analysis.