Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
IEEE Transactions on Nanotechnology
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes
Proceedings of the Conference on Design, Automation and Test in Europe
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Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current density and show 30-68% average write power savings and 4-41% reduction in MTJ current density in STT MRAM.