Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Spin angular momentum transfer in current-perpendicular nanomagnetic junctions
IBM Journal of Research and Development - Spintronics
Process Variation Tolerant 3T1D-Based Cache Architectures
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 45th annual Design Automation Conference
Storage-class memory: the next storage system technology
IBM Journal of Research and Development
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Energy- and endurance-aware design of phase change memory caches
Proceedings of the Conference on Design, Automation and Test in Europe
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Write-optimized reliable design of STT MRAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
High-performance low-energy STT MRAM based on balanced write scheme
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Improving energy efficiency of write-asymmetric memories by log style write
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Multi-level cell STT-RAM: is it realistic or just a dream?
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Asymmetry of MTJ switching and its implication to STT-RAM designs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
NVM duet: unified working memory and persistent store architecture
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for Universal memory. However, there are two challenges to using STT-RAM in memory system design: (1) the intrinsic variation in the storage element, the Magnetic Tunnel Junction (MTJ), and (2) the high write energy. In this paper, we present a physically based thermal noise model for simulating the statistical variations of MTJs. We have implemented it in HSPICE and validated it against analytical results. We demonstrate its use in setting the write pulse width for a given write error rate. We then propose two write-energy reduction techniques. At the device level, we propose the use of a low-MS ferromagnetic material that can reduce the write energy without sacrificing retention time. At the architecture level, we show that Invert Coding provides a 7% average reduction in the total write energy for the SPEC CPU2006 benchmark suite without any performance overhead.