Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
STT-RAM designs supporting dual-port accesses
Proceedings of the Conference on Design, Automation and Test in Europe
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It is well known that high write time/energy in STT MRAM are aggravated by the asymmetry in write currents for '0'→'1' and '1'→'0' transitions. This asymmetry is primarily due to the source degeneration of the access transistor during write. In this work, we propose a design methodology which avoids the source degeneration of the access transistor, leading to balanced switching times for '0'→'1' and '1'→'0' transitions. This is achieved by using an additional (negative) bit-line voltage and reduced word-line voltage. The proposed method reduces write time (by ~40%) and write energy (by 65%), enhances reliability of MTJ, and significantly improves tolerance to process variation. In the proposed scheme, source-line can be directly connected to ground signal leading to a compact cell layout.