Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors
IEEE Transactions on Computers
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Proceedings of the International Conference on Computer-Aided Design
High-performance low-energy STT MRAM based on balanced write scheme
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Dual pillar spin-transfer torque MRAMs for low power applications
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
A framework for simulating hybrid MTJ/CMOS circuits: atoms to system approach
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware optimization of STT MRAMs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Spin torque devices in embedded memory: model studies and design space exploration
Proceedings of the International Conference on Computer-Aided Design
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Spin-torque transfer magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It combines the desirable attributes of current memory technologies such as SRAM, DRAM, and flash memories (fast access time, low cost, high density, and non-volatility). It also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to a large number of cells to fail, severely affecting the yield of the memory array. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we performed a thorough analysis of the impact of design parameters on parametric failures due to process variations. To achieve high memory yield without incurring expensive technology modification, we developed an efficient design paradigm from circuit and/or architecture perspective--to improve the robustness and integration density. The proposed technique effectively relaxes or completely decouples the conflicting design requirements for read stability, writability and cell area. It can be used at an early stage of the design cycle for yield enhancement.