Dual pillar spin-transfer torque MRAMs for low power applications

Authors:
Niladri N. Mojumder;Xuanyao Fong;Charles Augustine;Sumeet K. Gupta;Sri Harsha Choday;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, Indiana;Purdue University, West Lafayette, Indiana;Purdue University, West Lafayette, Indiana;Purdue University, West Lafayette, Indiana;Purdue University, West Lafayette, Indiana;Purdue University, West Lafayette, Indiana
Venue:
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
Year:
2013

Citing 3
Cited 0

Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Three-Terminal Approach to Developing Spin-Torque Written Magnetic Random Access Memory Cells

IEEE Transactions on Nanotechnology
Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

IEEE Transactions on Nanotechnology

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Abstract

Electron-spin based data storage for on-chip memories has the potential for ultra-high density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we discuss the design challenges associated with spin-transfer torque (STT) MRAM in its state-of-the-art configuration. We propose an alternative bit cell configuration and three new genres of magnetic tunnel junction (MTJ) structures to improve STT-MRAM bit cell stabilities, write endurance, and reduce write energy consumption. The proposed multi-port, multi-pillar MTJ structures offer the unique possibility of electrical and spatial isolation of memory read and write. In order to realize ultralow power under process variations, we propose device, bit-cell and architecture level design techniques. Such design alternatives at multiple levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.