The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
Proceedings of the Conference on Design, Automation and Test in Europe
An overview of non-volatile memory technology and the implication for tools and architectures
Proceedings of the Conference on Design, Automation and Test in Europe
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Among all emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has shown many promising features such as fast access speed, nonvolatility, compatibility to CMOS process and excellent scalability. However, large process variations of both magnetic tunneling junction (MTJ) and MOS transistor severely limit the yield of STT-RAM chips. In this work, we present a recently proposed sensing technique called nondestructive self-reference read scheme (NSRS) to overcome the bit-to-bit variations in STT-RAM by leveraging the different dependencies of the high-resistance state of MTJs on the sensing current biases. Additionally, a few enhancement techniques including R-I curve skewing, yield-driven sensing current selection, and ratio matching are introduced to further improve the robustness of NSRS. The measurements of a 16Kb STT-RAM test chip shows that NSRS can significantly improve the chip yield by reducing sensing failures with high sense margin and low power consumptions.