Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
The salvage cache: a fault-tolerant cache architecture for next-generation memory technologies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Low-power dual-element memristor based memory design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
Proceedings of the Conference on Design, Automation and Test in Europe
Emerging sensing techniques for emerging memories
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Processor caches with multi-level spin-transfer torque ram cells
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement
Proceedings of the International Conference on Computer-Aided Design
Optimising Flash non-volatile memory using machine learning: a project overview
Proceedings of the Fifth Balkan Conference in Informatics
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Estimating MLC NAND flash endurance: a genetic programming based symbolic regression application
Proceedings of the 15th annual conference on Genetic and evolutionary computation
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
| Hi-index | 0.00 |
Novel nonvolatile memory technologies are gaining significant attentions from semiconductor industry in the competition of universal memory development. We used Spin-Transfer Torque Random Access Memory (STT-RAM) and Resistive Random Access Memory (R-RAM) as examples to discuss the implication of emerging nonvolatile memory for tools and architectures. Three aspects, including device and memory cell modeling, device/circuit co-design consideration and novel memory architecture, are discussed in details. The goal of these discussions is to design a high-density, low-power, highperformance nonvolatile memory with simple architecture and minimized circuit design complexity.