Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices

Authors:
Bo Zhao;Jun Yang;Youtao Zhang;Yiran Chen;Hai Li
Affiliations:
University of Pittsburgh;University of Pittsburgh;University of Pittsburgh;University of Pittsburgh;University of Pittsburgh
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Year:
2013

Citing 2
Cited 0

Nonvolatile memristor memory: device characteristics and design implications

Proceedings of the 2009 International Conference on Computer-Aided Design
An overview of non-volatile memory technology and the implication for tools and architectures

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck for further density improvement. In this article we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We elaborate the array design to ensure reliability, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 34% and 33% area for Memristor-RAM and STT-MRAM respectively, compared with corresponding dual-bitline arrays.