Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
A low-cost wear-leveling algorithm for block-mapping solid-state disks
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
CAVE: channel-aware buffer management scheme for solid state disk
Proceedings of the 2011 ACM Symposium on Applied Computing
SSD characterization: from energy consumption's perspective
HotStorage'11 Proceedings of the 3rd USENIX conference on Hot topics in storage and file systems
SAC: rethinking the cache replacement policy for SSD-based storage systems
Proceedings of the 5th Annual International Systems and Storage Conference
A multi-controller design for solid-state drives
Proceedings of the 2012 ACM Research in Applied Computation Symposium
A multi-controller architecture for high-performance solid-state drives
ACM SIGAPP Applied Computing Review
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
PMCD: a parallel multi-controller design for solid-state drives
Proceedings of the 2013 Research in Adaptive and Convergent Systems
An adaptive, low-cost wear-leveling algorithm for multichannel solid-state disks
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives
FAST'13 Proceedings of the 11th USENIX conference on File and Storage Technologies
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Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.