Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications
RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
Introduction to Algorithms, Third Edition
Introduction to Algorithms, Third Edition
FlashSim: A Simulator for NAND Flash-Based Solid-State Drives
SIMUL '09 Proceedings of the 2009 First International Conference on Advances in System Simulation
Modeling and simulating flash based solid-state disks for operating systems
Proceedings of the first joint WOSP/SIPEW international conference on Performance engineering
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
IEEE Transactions on Computers
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
IEEE Transactions on Computers
PMCD: a parallel multi-controller design for solid-state drives
Proceedings of the 2013 Research in Adaptive and Convergent Systems
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A solid-state drive consists of controllers and NAND flash memory chips, and each chip is controlled by one controller. Since each controller is responsible for a fixed number of chips, it can't control other chips that don't belong to it. Therefore, some idle controllers can't access other chips that don't belong to them, and it will reduce system performance. In this paper, we will propose a multi-controller architecture for high-performance solid-state drives. With the design, any chip will not be restricted to any specific controller, and any idle controller can access any chip. The experimental results show that the proposed method can improve system throughput of 25% when compared with traditional solid-state drives, and the incurred overhead is also reasonable.