eNVy: a non-volatile, main memory storage system
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Using data clustering to improve cleaning performance for plash memory
Software—Practice & Experience
Operating System Concepts
An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Energy-aware demand paging on NAND flash-based embedded storages
Proceedings of the 2004 international symposium on Low power electronics and design
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities
Journal of Systems Architecture: the EUROMICRO Journal
A flash-memory based file system
TCON'95 Proceedings of the USENIX 1995 Technical Conference Proceedings
Storage alternatives for mobile computers
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
A self-balancing striping scheme for NAND-flash storage systems
Proceedings of the 2008 ACM symposium on Applied computing
Architecture exploration of NAND flash-based multimedia card
Proceedings of the conference on Design, automation and test in Europe
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffer flush and address mapping scheme for flash memory solid-state disk
Journal of Systems Architecture: the EUROMICRO Journal
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Using NAND flash memory for executing large volume real-time programs in automotive embedded systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
What is the future of disk drives, death or rebirth?
ACM Computing Surveys (CSUR)
A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk
Microprocessors & Microsystems
Architectures and optimization methods of flash memory based storage systems
Journal of Systems Architecture: the EUROMICRO Journal
A low-cost wear-leveling algorithm for block-mapping solid-state disks
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
A hybrid flash translation layer with adaptive merge for SSDs
ACM Transactions on Storage (TOS)
CAVE: channel-aware buffer management scheme for solid state disk
Proceedings of the 2011 ACM Symposium on Applied Computing
Proceedings of the international conference on Supercomputing
A multi-controller design for solid-state drives
Proceedings of the 2012 ACM Research in Applied Computation Symposium
A multi-controller architecture for high-performance solid-state drives
ACM SIGAPP Applied Computing Review
Mapping granularity and performance tradeoffs for solid state drive
The Journal of Supercomputing
An adaptive, low-cost wear-leveling algorithm for multichannel solid-state disks
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Many mobile devices demand a large-capacity and high-performance storage system in order to store, retrieve, and process large multimedia data quickly. In this paper, we present a high-performance NAND flash-based storage system based on a multi-channel architecture. The proposed system consists of multiple independent channels, where each channel has multiple NAND flash memory chips. On this hardware, we investigate three optimization techniques to exploit I/O parallelism: striping, interleaving, and pipelining. By combining all the optimization techniques carefully, our system has shown 3.6 times higher overall performance compared to the conventional single-channel architecture.