A low-cost wear-leveling algorithm for block-mapping solid-state disks

  • Authors:

  • Li-Pin Chang;Li-Chun Huang

  • Affiliations:

  • National Chiao-Tung University, Hsin-Chu, Taiwan ROC;National Chiao-Tung University, Hsin-Chu, Taiwan ROC

  • Venue:
  • Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
  • Year:
  • 2011

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Abstract

Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wear-leveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.