An adaptive, low-cost wear-leveling algorithm for multichannel solid-state disks

  • Authors:

  • Li-Pin Chang;Tung-Yang Chou;Li-Chun Huang

  • Affiliations:

  • National Chiao-Tung University, Hsinchu, Taiwan;National Chiao-Tung University, Hsinchu, Taiwan;National Chiao-Tung University, Hsinchu, Taiwan

  • Venue:
  • ACM Transactions on Embedded Computing Systems (TECS)
  • Year:
  • 2013

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Abstract

Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any portions of flash memory from being retired prematurely. Modern solid-state disks must consider wear evenness at both block and channel levels. This study first presents a block-level wear-leveling method whose design has two new ideas. First, the proposed method reuses the intelligence available in flash-translation layers so it does not require any new data structures. Second, it adaptively tunes the threshold of block-level wear leveling according to the runtime write pattern. This study further introduces a new channel-level wear-leveling strategy, because block-level wear leveling is confined to a channel, but realistic workloads do not evenly write all channels. The proposed method swaps logical blocks among channels for achieving an eventually-even state of channel lifetimes. A series of trace-driven simulations show that our wear-leveling method outperforms existing approaches in terms of wear evenness and overhead reduction.