Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
An Efficient NAND Flash File System for Flash Memory Storage
IEEE Transactions on Computers
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture
IEEE Computer Architecture Letters
System software for flash memory: a survey
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Software controlled cell bit-density to improve NAND flash lifetime
Proceedings of the 49th Annual Design Automation Conference
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime
Proceedings of the Conference on Design, Automation and Test in Europe
Wear unleveling: improving NAND flash lifetime by balancing page endurance
FAST'14 Proceedings of the 12th USENIX conference on File and Storage Technologies
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This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.