Introduction to algorithms
An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
An efficient management scheme for large-scale flash-memory storage systems
Proceedings of the 2004 ACM symposium on Applied computing
Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
Efficient identification of hot data for flash memory storage systems
ACM Transactions on Storage (TOS)
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A flash-memory based file system
TCON'95 Proceedings of the USENIX 1995 Technical Conference Proceedings
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Flash memories: successes and challenges
IBM Journal of Research and Development
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 46th Annual Design Automation Conference
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
IEEE Transactions on Computers
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FAST: an efficient flash translation layer for flash memory
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
A flash compression layer for SmartMedia card systems
IEEE Transactions on Consumer Electronics
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Due to its remarkable access performance, shock resistance, and costs, NAND flash memory is now widely adopted in a variety of computing environments, especially in mobile devices such as smart phones, media players and electronic book readers. For the consideration of costs, low-cost embedded flash storages such as flash memory cards are often employed on such devices. Different from solid-state disks, the RAM buffer equipped on low-cost embedded flash storages are very small, for example, limited under several dozens of kilobytes, despite of the rapidly growing capacity of the storages. The significance of effectively utilizing the very limited on-device RAM buffers of embedded flash storages is therefore highlighted, and a novel design of scalable flash management schemes is needed to tackle the new access constraints of MLC NAND flash memory. In this work, a highly scalable design of the flash translation layer is presented with the considerations of the on-device RAM size, user access patterns, address-mapping-information caching and MLC access constraints. Through a series of experiments, it is verified that, with appropriate settings of cache sizes, the proposed management scheme provides comparable performance results to prior arts with much lower requirements on the on-device RAM. In other words, the proposed scheme suggests a strategy to make better use of the on-device RAM, and is suitable for embedded flash storages.