SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
An efficient management scheme for large-scale flash-memory storage systems
Proceedings of the 2004 ACM symposium on Applied computing
Efficient management for large-scale flash-memory storage systems with resource conservation
ACM Transactions on Storage (TOS)
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Performance improvement of block based NAND flash translation layer
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Communications of the ACM - Web science
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
A time-predictable system initialization design for huge-capacity flash-memory storage systems
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
A survey of Flash Translation Layer
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 46th Annual Design Automation Conference
RNFTL: a reuse-aware NAND flash translation layer for flash memory
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
Implementation strategy for downgraded flash-memory storage devices
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
BLog: block-level log-block management for NAND flash memorystorage systems
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
FTL2: a hybrid flash translation layer with logging for write reduction in flash memory
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Compiler directed write-mode selection for high performance low power volatile PCM
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
A survey of address translation technologies for flash memories
ACM Computing Surveys (CSUR)
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The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping in the Flash Translation Layer (FTL) design. This paper proposes a novel Demand-based block-level Address mapping scheme with two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without sacrificing too much system response time. In our technique, the block-level address mapping table is stored in fixed pages (called translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand block-level address mapping information. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages into RAM. In such a way, address mapping information for both sequential accesses and most-frequently-accessed translation pages can be found in the cache, and therefore, the system response time can be improved. We conduct experiments on a mixture of real-world and synthetic traces. The experimental results show that our technique can significantly reduce the RAM footprint while the average response time is kept well under control. Moreover, our technique shows big improvement on wear-leveling compared with the previous work.