An efficient management scheme for large-scale flash-memory storage systems
Proceedings of the 2004 ACM symposium on Applied computing
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation
ISORC '06 Proceedings of the Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Performance improvement of block based NAND flash translation layer
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Block recycling schemes and their cost-based optimization in nand flash memory based storage system
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
The Behavior Analysis of Flash-Memory Storage Systems
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
A survey of Flash Translation Layer
Journal of Systems Architecture: the EUROMICRO Journal
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
An efficient method for record management in flash memory environment
Journal of Systems Architecture: the EUROMICRO Journal
BLog: block-level log-block management for NAND flash memorystorage systems
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
FTL2: a hybrid flash translation layer with logging for write reduction in flash memory
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
A space reuse strategy for flash translation layers in SLC NAND flash memory storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cooperating virtual memory and write buffer management for flash-based storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A survey of address translation technologies for flash memories
ACM Computing Surveys (CSUR)
Hi-index | 0.00 |
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a merge operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.