A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A design for high-performance flash disks
ACM SIGOPS Operating Systems Review - Systems work at Microsoft Research
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Energy-efficient and performance-enhanced disks using flash-memory cache
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Performance improvement of block based NAND flash translation layer
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
The Behavior Analysis of Flash-Memory Storage Systems
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Deterministic service guarantees for nand flash using partial block cleaning
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
RNFTL: a reuse-aware NAND flash translation layer for flash memory
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Proceedings of the 47th Design Automation Conference
A file-system-aware FTL design for flash-memory storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
A set-based mapping strategy for flash-memory reliability enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Minimizing write activities to non-volatile memory via scheduling and recomputation
SASP '10 Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors (SASP)
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DHeating: dispersed heating repair for self-healing NAND flash memory
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Hi-index | 0.00 |
Log-block-based FTL (Flash Translation Layer) schemes have been widely used to manage NAND flash memory storage systems in industry. In log-block-based FTLs, a few physical blocks called log blocks are used to hold all page updates from a large amount of data blocks. Frequent page updates in log blocks introduce big overhead so log blocks become the system bottleneck. To address this problem, this paper presents a block-level log-block management scheme called BLog (Block-level Log-Block Management). In BLog, with the block level management, the update pages of a data block can be collected together and put into the same log block as much as possible; therefore, we can effectively reduce the associativities of log blocks so as to reduce the garbage collection overhead. We also propose a novel partial merge operation called reduced-order merge by which we can effectively postpone the garbage collection of log blocks so as to maximally utilize valid pages and reduce unnecessary erase operations in log blocks. Based on BLog, we design an FTL called BLogFTL for MLC NAND flash. We conduct experiments on a mixture of real-world and synthetic traces. The experimental results show that our scheme outperforms the previous log-block-based FTLs for MLC NAND flash.