An adaptive two-level management for the flash translation layer in embedded systems

  • Authors:

  • Chin-Hsien Wu;Tei-Wei Kuo

  • Affiliations:

  • National Taiwan University, Taipei, Taiwan, ROC;National Taiwan University, Taipei, Taiwan, ROC

  • Venue:
  • Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2006

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Abstract

While the capacity of flash-memory storage systems keeps increasing significantly, effective and efficient management of flash-memory space has become a critical design issue! Different granularities in space management impose different management costs and mapping efficiency. In this paper, we explore an address translation mechanism that can dynamically and adaptively switch between two granularities in the mapping of logical block addresses into physical block addresses in flash memory management. The objective is to provide good performance in address mapping and space utilization and, at the same time, to have the memory space requirements, and the garbage collection overhead under proper management. The experimental results show that the proposed adaptive mechanism could provide significant performance improvement over the well-known coarsegrained management mechanism NFTL (NAND Flash Translation Layer) over realistic workloads.