ExLRU: a unified write buffer cache management for flash memory

  • Authors:

  • Liang Shi;Jianhua Li;Chun Jason Xue;Chengmo Yang;Xuehai Zhou

  • Affiliations:

  • City University of Hong Kong, Kowloon, Hong Kong and University of Science and Technology of China, Hefei, China;City University of Hong Kong, Kowloon, Hong Kong and University of Science and Technology of China, Hefei, China;City University of Hong Kong, Kowloon, Hong Kong;University of Delaware, Delaware, DE, USA;University of Science and Technology of China, Hefei, China

  • Venue:
  • EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
  • Year:
  • 2011

Quantified Score

Hi-index 0.00

Visualization

Abstract

NAND flash memory has been widely adopted in embedded systems as secondary storage. Yet the further development of flash memory strongly hinges on the tackling of its inherent implausible characteristics, including read and write speed asymmetry, inability of in-place update, and performance harmful erase operations. While Write Buffer Cache (WBC) has been proposed to enhance the performance of write operations, the development of a unified WBC management scheme that is effective for diverse types of access patterns is still a challenging task. In this paper, a novel WBC management scheme named Expectation-based LRU (ExLRU) is proposed to improve the performance of write operations while at the same time reducing the number of erase operations on flash memory. ExLRU accurately maintains access history information in WBC, based on which a new cost model is constructed to select the data with minimum write cost to be written to flash memory. An efficient ExLRU implementation with negligible hardware overhead is further developed. Simulation results show that ExLRU outperforms state-of-art WBC management schemes under various workloads.