A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
System software for flash memory: a survey
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
FAB: flash-aware buffer management policy for portable media players
IEEE Transactions on Consumer Electronics
Recently-evicted-first buffer replacement policy for flash storage devices
IEEE Transactions on Consumer Electronics
ExLRU: a unified write buffer cache management for flash memory
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
h-Buffer: an adaptive buffer management scheme for flash-based storage devices
DASFAA'12 Proceedings of the 17th international conference on Database Systems for Advanced Applications
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
| Hi-index | 0.00 |
Using device write buffers is a promising technique to improve the write performance of solid-state disks. The write buffer not only reduces the write traffic to the flash but also produces large and sequential write bursts to the underlying flash translation layer. This study proposes a new buffer design consisting of a replacement policy and a write-back policy. This buffer monitors how the host workload stresses the flash translation layer upon garbage collection, and dynamically adjusts its replacement and write-back strategies for a good balance between write sequentiality and traffic reduction. Experimental results show that the proposed buffer design outperformed existing approaches by up to 20% under various workloads and flash translation algorithms.