An adaptive flash translation layer for high-performance storage systems

  • Authors:

  • Chin-Hsien Wu;Hsin-Hung Lin;Tei-Wei Kuo

  • Affiliations:

  • Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
  • Year:
  • 2010

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Abstract

While the capacity of flash-memory storage systems keeps increasing significantly, an effective and efficient management of flash-memory space has become a critical design issue. Different granularities in space management impose different management costs and mapping efficiency. In this paper, we will explore an address translation mechanism (AddrTM) that can dynamically and adaptively switch between different granularities in the mapping of logical block addresses into physical block addresses in flash-memory management. The objective is to provide high performance in address mapping and space utilization and, at the same time, to have the main memory requirements, the garbage collection overhead, and the system initialization time under proper management. The experimental results show that the proposed adaptive mechanism can provide better performance improvement and practicability than other well-known coarse-grained management mechanisms over realistic workloads.