An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Storing a persistent transactional object heap on flash memory
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
CFLRU: a replacement algorithm for flash memory
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Competitive analysis of flash-memory algorithms
ESA'06 Proceedings of the 14th conference on Annual European Symposium - Volume 14
Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design
Proceedings of the 44th annual Design Automation Conference
A NOR Emulation Strategy over NAND Flash Memory
RTCSA '07 Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Write activity reduction on flash main memory via smart victim cache
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Demand-based block-level address mapping in large-scale NAND flash storage systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A reliable MTD design for MLC flash-memory storage systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Proceedings of the 48th Design Automation Conference
A version-based strategy for reliability enhancement of flash file systems
Proceedings of the 48th Design Automation Conference
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A caching-oriented management design for the performance enhancement of solid-state drives
ACM Transactions on Storage (TOS)
An adaptive file-system-oriented FTL mechanism for flash-memory storage systems
ACM Transactions on Embedded Computing Systems (TECS)
Working-set-based address mapping for ultra-large-scaled flash devices
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Modern flash technologies: a flash translation layer perspective
International Journal of High Performance Systems Architecture
ACM Transactions on Embedded Computing Systems (TECS)
A DRAM-flash index for native flash file systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Adaptive range-based address mapping for the flash storage devices with explosive capacity
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication
Migration-based hybrid cache design for file systems over flash storage devices
ACM SIGAPP Applied Computing Review
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Cost has been a major driving force in the development of the flash memory technology, but has also introduced serious challenges on reliability and performance for future products. In this work, we propose a commitment-based management strategy to resolve the reliability problem of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of multi-level-cell flash memory chips.