ACM Transactions on Storage (TOS)
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An efficient B-tree layer implementation for flash-memory storage systems
ACM Transactions on Embedded Computing Systems (TECS)
RNFTL: a reuse-aware NAND flash translation layer for flash memory
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A caching-oriented management design for the performance enhancement of solid-state drives
ACM Transactions on Storage (TOS)
FTL2: a hybrid flash translation layer with logging for write reduction in flash memory
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
A space reuse strategy for flash translation layers in SLC NAND flash memory storage systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
While flash memory has been widely adopted for various embedded systems, space efficiency with reasonable performance has become a critical issue for the design of the flash-memory translation layer. The target of this paper is to improve the performance of existing designs by proposing a search-tree-like caching mechanism for efficient address translation. A replacement strategy with a low time complexity is presented to monitor the access status of recently used LBA's. The proposed caching mechanism and replacement strategy were shown being highly effective in the reducing of the address translation time over popular translation layer designs, such as NAND, where realistic workloads were used for experiments.