An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design
Proceedings of the 44th annual Design Automation Conference
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead
MSST '11 Proceedings of the 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies
FAST: an efficient flash translation layer for flash memory
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Joint management of RAM and flash memory with access pattern considerations
Proceedings of the 49th Annual Design Automation Conference
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
3D-FlashMap: a physical-location-aware block mapping strategy for 3D NAND flash memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Even though 3D flash memory presents a grand opportunity for huge-capacity non-volatile memory, it suffers from serious program disturb problems. Different from the past efforts in error correction codes or the work in trading the space utilization with reliability, we propose a disturb-alleviation scheme that can alleviate the negative effects caused by program disturb, especially inside a block, without introducing extra overheads on encoding or storing of extra redundant data. In particular, a methodology is proposed to reduce the data error rate by distributing unavoidable disturb errors over the flash-memory space of invalid data, with the considerations of the physical organization of 3D flash memory. A series of experiments was conducted based on real multi-layer 3D flash chips, and it showed that the proposed scheme could significantly enhance the reliability of 3D flash memory.