MFTL: A Design and Implementation for MLC Flash Memory Storage Systems

  • Authors:

  • Jen-Wei Hsieh;Chung-Hsien Wu;Ge-Ming Chiu

  • Affiliations:

  • National Taiwan University of Science and Technology, Taiwan;InCOMM Technologies Corporation, Taiwan;National Taiwan University of Science and Technology, Taiwan

  • Venue:
  • ACM Transactions on Storage (TOS)
  • Year:
  • 2012

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Abstract

NAND flash memory has gained its popularity in a variety of applications as a storage medium due to its low power consumption, nonvolatility, high performance, physical stability, and portability. In particular, Multi-Level Cell (MLC) flash memory, which provides a lower cost and higher density solution, has occupied the largest part of NAND flash-memory market share. However, MLC flash memory also introduces new challenges: (1) Pages in a block must be written sequentially. (2) Information to indicate a page being obsoleted cannot be recorded in its spare area due to the limitation on the number of partial programming. Since most of applications access NAND flash memory under FAT file system, this article designs an MLC Flash Translation Layer (MFTL) for flash-memory storage systems which takes constraints of MLC flash memory and access behaviors of FAT file system into consideration. A series of trace-driven simulations was conducted to evaluate the performance of the proposed scheme. Although MFTL is designed for MLC flash memory and FAT file system, it is applicable to SLC flash memory and other file systems as well. Our experiment results show that the proposed MFTL could achieve a good performance for various access patterns even on SLC flash memory.