The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
Proceedings of the 36th annual international symposium on Computer architecture
Proceedings of the international conference on Supercomputing
DRAMSim2: A Cycle Accurate Memory System Simulator
IEEE Computer Architecture Letters
Computer Architecture, Fifth Edition: A Quantitative Approach
Computer Architecture, Fifth Edition: A Quantitative Approach
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In this paper, we propose a three dimensional storage-on-chip design that provides systems with high integration. The main memory and disk storage are stacked on-chip with through silicon vias. We analyse implementation feasibility, a 3D chip with multiple layers of DRAM and NAND storage is modelled accordingly. We use a sophisticated simulation toolset to analyse the performance of various architectures. Full system evaluation using SPLASH-2 benchmarks shows that, compared to conventional off-chip main memory and disk storage, our design can reduce the overall execution time by 38.3% on average.