Design considerations for MRAM
IBM Journal of Research and Development - Spintronics
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
Write endurance in flash drives: measurements and analysis
FAST'10 Proceedings of the 8th USENIX conference on File and storage technologies
How i learned to stop worrying and love flash endurance
HotStorage'10 Proceedings of the 2nd USENIX conference on Hot topics in storage and file systems
Optimizing NAND flash-based SSDs via retention relaxation
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Revisiting storage for smartphones
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
Analytic modeling of SSD write performance
Proceedings of the 5th Annual International Systems and Storage Conference
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Flash memory has been an active topic of research in recent years, but hard information about the parameters and behavior of both flash chips and SSDs has been difficult to obtain for those outside of the industry. In this paper several misconceptions found in the literature are addressed, in order to enable future researchers to avoid some of the errors found in prior work. We examine the following topics: flash device parameters such as page and erase block size, speed, and reliability, as well as flash translation layer (FTL) requirements and behavior under random and sequential I/O. We have endeavored to find public sources for our claims, and provide experimental evidence in several cases. In doing so, we provide previously unpublished results showing the viability of random writes on commodity SSDs when restricted to a sufficiently small portion of the logical address space.