A dual-grained FTL for flash memory

  • Authors:

  • Junjie Wang;Lihua Yue;Peiquan Jin;Rui Wang

  • Affiliations:

  • School of Computer Science and Technology, University of Science and Technology of China, Hefei, China;School of Computer Science and Technology, University of Science and Technology of China, Hefei, China;School of Computer Science and Technology, University of Science and Technology of China, Hefei, China;School of Computer Science and Technology, University of Science and Technology of China, Hefei, China

  • Venue:
  • DASFAA'12 Proceedings of the 17th international conference on Database Systems for Advanced Applications
  • Year:
  • 2012

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Abstract

Flash memory has been widely used in both embedded devices and enterprise storage devices, due to its specific characteristics such as small size, light weight, high speed, shock resistance, and less energy consumption. However, in order to deal with the special limitation of flash memory, i.e., erase-before-write, an intermediate software layer called flash translation layer (FTL) was employed in modern flash-based disks to map logical page addresses from the file system to physical page addresses used in flash memory. However, most existing FTL schemes suffer from the overhead of small random writes and merge operations, especially full merges. In this paper, we proposed a novel FTL named DGFTL (Dual-Grained FTL), which divides flash memory into two regions, namely a page region and a block region. DGFTL uses new algorithms to manage the dual-grained flash memory and can effectively transfer small random writes into sequential ones. This leads to more efficient switch merges and less costly full merges and partial merges. Our experimental results show that DGFTL reduces the count of erase operation by more than 50% over some existing flash memory management techniques.