BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
A case for flash memory ssd in enterprise database applications
Proceedings of the 2008 ACM SIGMOD international conference on Management of data
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Migrating server storage to SSDs: analysis of tradeoffs
Proceedings of the 4th ACM European conference on Computer systems
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
Evaluation of disk-level workloads at different time-scales
IISWC '09 Proceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC)
PUD-LRU: An Erase-Efficient Write Buffer Management Algorithm for Flash Memory SSD
MASCOTS '10 Proceedings of the 2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
BPAC: An adaptive write buffer management scheme for flash-based Solid State Drives
MSST '10 Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)
FAB: flash-aware buffer management policy for portable media players
IEEE Transactions on Consumer Electronics
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More and more enterprise servers storage systems are migrating toward flash based drives (Solid State Drives) thanks to their attractive characteristics. They are lightweight, power efficient and supposed to outperform traditional disks. The two main constraints of flash memories are: 1) the limited number of achievable write operations beyond which a given cell can no more retain data, and 2) the erase-before-write rule decreasing the write performance. A RAM cache can help to reduce this problem; they are mainly used to increase performance and lifetime by absorbing flash write operations. RAM caches being very costly, their dimensioning is critical. In this paper, we explore some OLTP I/O workload characteristics with regards to flash memory cache systems structure and configuration. We try, throughout I/O workload analysis to reveal some important elements to take into account to allow a good dimensioning of those embedded caches.