Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Error Control Coding, Second Edition
Error Control Coding, Second Edition
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving NAND Flash Based Disk Caches
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories
ETS '08 Proceedings of the 2008 13th European Test Symposium
Exploiting half-wits: smarter storage for low-power devices
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
Working-set-based address mapping for ultra-large-scaled flash devices
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
ACM Transactions on Embedded Computing Systems (TECS)
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
A DRAM-flash index for native flash file systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an algorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive '01' and '10' bit-patterns during error control coding. We show that the algorithm does not change the error correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33% of write energy and 31% of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%.