Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Optimal Spare Utilization in Repairable and Reliable Memory Cores
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Built-In Self-Repair Scheme for NOR-Type Flash Memory
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Working-set-based address mapping for ultra-large-scaled flash devices
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Embedded Computing Systems (TECS)
A DRAM-flash index for native flash file systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floating-gate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as Error Correction Code (ECC), Redundancy or Threshold Voltage (VT) Analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed.